Generally, a semiconductor device is fabricated by repeatedly performing various fabrication processes on a silicon wafer. Semiconductor fabrication processes include oxidation, masking, photoresist coating, etching, diffusion and layer formation processes with respect to a wafer which is a material of a semiconductor device. Before and after the aforementioned processes, other processes such as cleaning, dry and testing processes are additionally performed. Specifically, an etching process is one of the important processes of forming a pattern on a wafer. A photolithography process is performed by an etching process and a photoresist coating process. After a wafer is coated with photoresist of photosensitivity and a pattern is transmitted to the wafer, etching is performed along the pattern, thereby providing a device with predetermined physical properties according to the pattern.
An etching process is largely divided into wet etching and dry etching. Wet etching is performed by a method of soaking a wafer in a wet etching container including a chemical substance to effectively remove the uppermost layer of the wafer, a method of spraying the chemical substance on the surface of the wafer, or a method of flowing a chemical material onto the wafer tilted at a predetermined angle.
Examples of dry etching include plasma etching using a gaseous etching gas, ion beam etching, reactive ion etching, and the like. A reactive ion etching process is performed by supplying an etching gas into a reaction chamber, ionizing the gas, and accelerating the ionized gas on the surface of a wafer, so as to physically and chemically remove the uppermost layer of the surface of the wafer. Reactive ion etching is widely used because etching may be easily controlled, productivity may be high, and formation of a pattern with a size of about 1 μm may be possible.
The parameters for uniform etching in the reactive ion etching process include the thickness and density of a layer to be etched, the energy and temperature of an etching gas, the adhesiveness of photoresist, the condition of the surface of a wafer, and the uniformity of the etching gas. Specifically, the control of radio frequency (RF), which is a driving force to ionize an etching gas and accelerate the ionized gas on the surface of a wafer to be etched, is an important parameter. The control of RF is further considered as a parameter to be directly and easily controlled while an etching process is actually performed.
For a semiconductor device requiring the design rule of 0.15 μm or less, a dry etching method is generally applied by using a plasma reaction gas.
A plasma-enhanced chemical vapor deposition (PECVD) apparatus and a dry etching apparatus commonly use a plasma gas and have a similar interior constitution. Each processing apparatus includes a chamber for processing a semiconductor substrate, an electrode, to which RF power is applied, for generating plasma of a reaction gas to be supplied to the chamber, and a chuck for supporting the semiconductor substrate.
As examples of the aforementioned processing apparatuses, U.S. Pat. No. 5,510,297 (issued to Telford, et al.) and U.S. Pat. No. 5,565,382 (issued to Tseng, et al.) disclose an apparatus for forming a layer on a semiconductor substrate supported on a susceptor, by using a plasmatized reaction gas; and U.S. Pat. No. 5,259,922 (issued to Yamano, et al.) and U.S. Pat. No. 6,239,036 (issued to Arita, et al.) disclose an apparatus for etching a layer on a semiconductor substrate, by using a plasmatized reaction gas formed by RF power.
In the aforementioned semiconductor etching apparatus, an edge ring is positioned around an edge of the upper surface of the chuck which is positioned to support the semiconductor substrate in the chamber. The edge ring concentrates a plasmatized reaction gas formed in the chamber to the semiconductor substrate. The edge ring is positioned to surround an edge of the semiconductor substrate supported by the chuck and allows the plasmatized reaction gas to be uniformly supplied to the semiconductor substrate.
The aforementioned semiconductor etching apparatus performs an etching process, by allowing an etching gas to flow in a high vacuum condition, and to form plasma. When a layer formed on a wafer is etched, a great amount of heat is inevitably generated, so that a temperature of the wafer increases. The temperature rise may seriously affect the etching uniformity, thereby obstructing the process. During the etching process, for cooling, a coolant flows through an electro static chuck (ESC) positioned at a lower position, thereby continuously maintaining a wafer at a uniform temperature. Further, for smooth exchange of heat between the wafer and ESC in a high vacuum, helium (He) is allowed to flow under the backside of the wafer. Then, to prevent the wafer from deviating by the pressure of helium, high power is applied to the ESC so that a coulomb force is generated and the wafer is chucked. Then, when an etching gas enters the chamber, the RF power is applied to form plasma in the chamber. The plasma includes electrons, radicals and ions. The ions with high reactivity are drawn to the wafer by bias power applied to the ESC and react with a layer material formed on the wafer, so that an etching process is performed. During the etching process, polymers are inevitably generated as byproducts of the reaction. Most polymers are discharged to the outside by a turbo pump positioned at a lower position in the chamber but some remain on parts in the chamber.
FIG. 1 is a view illustrating a structure of a prior art ESC assembly module.
A chamber is provided with an ESC 10 for selectively holding a wafer being entered and positioned. The ESC 10 includes a lower electrode part to which RF power is applied and allows an ESC assembly to be moved up and down. An edge ring 12 is positioned at a stepped portion formed on the ESC 10 and induces discharge of polymers and the like being generated during a process. A lower quartz ring 14 is positioned under the edge ring 12 and is extended to protrude out of an outer side of a stepped portion of the ESC 18. An upper quartz ring 16 is positioned on the lower quartz ring 14 and surrounds the edge ring 12. An insulation ring 18 is positioned to support the lower quartz ring 14 and surrounds the edge of the ESC 10 to protect a sidewall of the ESC 10 upon a plasma reaction.
The prior art ESC assembly module comprises a combination of many parts generally including the edge ring 12, the lower quartz ring 14, the upper quartz ring 16 and the insulation ring 18 at the side of the ESC 10. The parts and the ESC 10 are assembled at connection tolerance. That is, these parts are not coupled with the ESC 10 but are simply placed on a protruding portion at a lower end of the edge of ESC 10, so as to be in contact with the ESC 10 and are made of aluminum and anodizing materials. The ESC 10 and the edge ring 12 are assembled to have slight gaps at assembly tolerance. Although the lower part of the edge ring 12 is in contact with the ESC 10, fine gaps exist therebetween, due to their respective roughness upon metal to metal contact. A vacuum path is formed along the gaps. Before passing the upper quartz ring 16, some polymers generated during the process move to the lower position, along the vacuum path formed at the side of the ESC 10. Since the side of the ESC 10 is continuously cooler than the edge ring 12 being exposed to the plasma and having high temperature, the polymers are likely to remain at the sidewall of the ESC 10, as illustrated in FIG. 2. The polymers accumulated at the sidewall of the ESC 10 are unstable. Accordingly, the polymers remaining at the sidewall of the ESC 10 move up to the upper surface of the ESC 10 by a vortex caused when a wafer is dechucked or transferred after the process. When the polymers remain on the upper surface of the ESC 10, the wafer cannot be secured against the ESC 10 upon the wafer chucking, thereby causing helium to leak at the backside of the wafer, to cause an error. When an error is caused, the wafer is not cooled and the temperature suddenly rises. Then, the impedance of the chamber is changed and the plasma is not stabilized, thereby causing a failure in the etching process.